Field-Programmable Gate Arrays Engineer

About the role

Celos Lab is seeking a contract FPGA Engineer to join its hybrid team in Lagos State, Nigeria. You will work on designing and optimizing FPGA‑based architectures that support the company’s AI Cell Fabric vision for spatial and distributed AI workloads.

Key responsibilities

• Write, verify, and debug RTL code using Verilog or VHDL.
• Integrate digital signal processing blocks and implement DSP algorithms on FPGA platforms.
• Run simulations, hardware‑in‑the‑loop tests, and use logic analyzers to validate designs.
• Collaborate with AI systems and hardware teams to make architecture decisions and translate research concepts into robust implementations.

Required profile

• Strong background in RTL design and FPGA toolchains.
• Solid experience with digital signal processing and signal‑processing analysis.
• Hands‑on expertise debugging complex FPGA designs using simulation and embedded debug tools.
• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field, or equivalent practical experience.

Required skills

• Verilog and VHDL.
• FPGA ecosystems such as Xilinx/AMD and Intel/Altera, including synthesis and place‑and‑route tools.
• Performance optimization and timing analysis.
• Use of simulation environments, logic analyzers, and embedded debugging utilities.